1. Field of the Invention
The present invention relates to a display device and, more particularly, to a display device including a plurality of driver ICs that are cascade connected.
2. Description of Related Art
Display panels have lately become even larger and a display device that is driven by a plurality of cascade-connected driver ICs draws attention.
Such a display device which is typically configured in prior art as is shown in FIG. 12 is generally known (for example, refer to Japanese Patent Document Cited 1).
The display device shown in FIG. 12 comprises an LCD controller which outputs start pulses, visual data, and a clock and a plurality of driver ICs, each of which captures visual data synchronized with a clock in response to a start pulse and drives a display panel, based on the visual data.
A driver IC starts to capture data in response to a start pulse supplied from the LCD controller and captures the data in synchronization with a clock signal. Upon completion of capturing the data, the driver IC outputs a start pulse to the next driver IC.
In this manner, one driver IC generates a start pulse to the next stage driver IC, and the plurality of driver ICs capture data sequentially and drive the display panel.
[Japanese Patent Document Cited 1]
Japanese Published Unexamined Patent Application No. Hei 11-194748
In the liquid crystal display device shown as a prior art example, data, a clock, and a start signal are supplied to a first-stage deriver IC from the LCD controller, wherein the start signal is supplied to the first-stage driver only once for one horizontal period, whereas, to second-stage and subsequent driver ICs, the data and clock are supplied from the LCD controller and a start signal is supplied from the preceding-stage driver IC. Thus, the second-stage and subsequent driver ICs capture data, synchronized with the clock signal and based on the start signal generated by the preceding-stage driver IC. For the second-stage and subsequent driver ICs, the data and clock are synchronized because their transmission paths are substantially the same, but the data/clock and the start signal which is generated by a driver internal circuit are not synchronized. This causes a problem that erroneous data is captured when timing misalignment between the data/clock and the start signal occurs. This problem is significant at higher clock frequencies.